1. Technical Field
This disclosure is related to the manufacture of semiconductor devices, and in particular, the manufacture of flip-chip structures on semiconductor wafers.
2. Description of the Related Art
Semiconductor devices are packaged in a large variety of structures. A configuration that is used with increasing frequency in semiconductor packaging is the flip-chip. This term refers to a process and structure in which electrical contacts, e.g., solder balls, are placed on a semiconductor die in contact with contact pads of the die, forming a ball grid array (BGA) on the face of the die. The die is then placed active-side down on a carrier substrate with the solder balls in contact with “landing pads” of the substrate. Finally, in a reflow step, the solder balls are heated until they melt and form a solder joint between the contact pads of the die and the landing pads of the substrate. Such an arrangement can be used, for example, to bond a semiconductor chip directly to a circuit board, or to a chip carrier of a larger package that includes a redistribution layer and a second BGA with solder balls spaced at a coarser pitch to accommodate the spacing of landing pads on a circuit board.
In response to market pressure and technological advancement, circuit density in semiconductor devices continues to increase, resulting in tighter spacing between contact pads, and the need for finer pitch arrays, on devices that employ BGA structures. As array pitch is made finer, the solder balls must be made smaller to prevent short circuits between solder balls. This reduces the space between the semiconductor die and the substrate.
It should be noted that the coefficient of thermal expansion (CTE) of silicon is about 2.5 ppm/° C., while that of a typical package laminate base is around 17 ppm/° C. During operation, heat generated by operation of the integrated circuit in the die causes thermal expansion of the die and the substrate. Thermal mismatch between the die and the substrate results in shear stress on the solder joints of the BGA. Where larger solder balls are used, the solder joint itself can deform to a limited degree, permitting the substrate and die to expand at different rates without damage, but with smaller solder balls, the solder joints are less able to compensate, and joint failure can result. It has been found that as offset of the die from the substrate decreases, joint failure increases. However, maintaining a particular minimum offset imposes a minimum solder ball size, which in turn imposes a minimum pitch.
One solution to this problem is the formation of pillars on which smaller solder bumps are formed. FIG. 1 shows a flip-chip structure 100 that includes a semiconductor die 102 with a repassivation layer 110 positioned thereon. Openings 111 in the repassivation layer 110 expose contact pads 104 of the semiconductor die 102. Copper pillars 106 are formed on of the die 102 over, and in electrical contact with the contact pads 104, and solder bumps 108 are formed on the ends of the pillars 106. When this structure is placed with the solder bumps in contact with landing pads of a substrate, the copper pillars 106 do not reflow with the solder bumps 108, so the die 102 remains spaced apart from the substrate by the pillars. During operation, differences in expansion can be accommodated by the copper pillars 106, thereby increasing the reliability of the solder joints.
FIGS. 2 and 3 show respective stages in one known process for producing pillar-bumps. As shown in FIG. 2, a seed layer 112 or under-bump metallic layer (UBM), typically of Ti/Cu or Ti/W/Cu, is deposited over the repassivation layer 110 and contact pads 104. A resist layer 114 is then deposited over the seed layer 112 and patterned to form openings 116 that expose the seed layer 112 in positions corresponding to the contact pads 104. Copper is then plated onto the seed layer 112 in the openings 115 to form the copper pillars 106. The resist layer 114 is then stripped away, leaving the pillars 106, after which a layer of flux 118 is deposited over the substrate, including the pillars 106. Solder balls 120 are then positioned on the copper pillars 106 and pressed into the flux layer 118, which holds them in position.
The wafer 100 is then heated until the solder balls 120 reflow and form the bumps 108, the flux serving to exclude oxygen from the solder bond. Finally, the remaining flux 118 is cleaned from the wafer 100 and an etch is performed to remove the exposed portions of the seed layer 112, leaving pillar bumps on the wafer as shown in FIG. 1.
The process described above is useful for forming pillar bumps at pitches of greater than around 200 μm. At finer pitches, the various known methods for positioning solder balls in “ball drop” operations become less reliable. Lack of a single solder ball can render useless the entire device. At the same time, the number of contact pads that can be formed on a semiconductor die of a given size increases in inverse relation to the pitch size. Semiconductor devices can have 1-3000 contacts or more. Failure to properly position one solder ball in 10,000 could result in a rejection rate of greater than 10%.
For these reasons, at pitches that are finer than around 200 μm, solder paste is commonly used, deposited on the Cu pillars 106 in the openings 116 of FIG. 2, after which the wafer is heated to reflow the solder paste. At even finer pitches, especially below 100 μm, solder paste becomes unreliable, inasmuch as the size of the metallic particles of the paste become a factor, and because of an increasing tendency to leave voids. It is therefore most common, at such pitch levels, to deposit solder material by electroplating, as described with reference to FIGS. 4 and 5, which show a wafer 130. The wafer 130 includes a semiconductor substrate 103 that is similar in structure to the substrate 102 of FIGS. 1-3 except that the contact pads 105 are at a finer pitch than those shown in FIGS. 1-3. The process follows the same steps described above with reference to FIG. 2. Following the plating process used to form the Cu pillars 107, a second electroplating step is performed to deposit a quantity of solder 122 on the tops of the pillars 107, as shown in FIG. 4. The resist layer 114 is then removed, the seed layer 112 is removed by etching, and the solder 122 is reflowed to form the bumps 124 on the Cu pillars 107, forming pillar bumps 128, as shown in FIG. 5. Following formation of the pillar bumps 128, the wafer 103 is cut into a plurality of individual dice, each of which is then positioned facing a receiving support structure such as, e.g., a chip carrier laminate, with the solder bumps 124 in contact with contact pads of the carrier. The solder is again reflowed to bond the die to the laminate.
A particular problem with this approach is that the solder electroplating process is generally limited to plating a binary alloy. In other words, a plated solder can be an alloy of no more than two metals. Alloys of tin and lead are most commonly plated.